1. Field of the Invention
The present invention relates generally to a minimum leading edge blanking (MLEB) signal generator, and more particularly, to an MLEB signal generator and a method for generating an MLEB signal adapted for blanking a peak high voltage signal for avoiding a misoperation.
2. The Prior Arts
Recently, high performance chips lead the trend of further development, and the chip processing technologies are being developed toward smaller sizes, e.g., from 0.8 μm to 0.18 μm, 0.13 μm, or even 65 nm. Correspondingly, different chip processing technologies requires particular operation voltages, e.g., 5.0V, 3.3V, 1.8V, or 1.2V. Accordingly, a power source management chip which is capable of converting different input voltages into a suitable output power or output voltage is often employed in the chip processing technologies.
In a typical power source management chip, a buck DC-DC converter is often used for providing an output voltage lower than the input voltage, e.g., converting 5.0V to 3.3V, or converting 3.3V to 1.8V. An application circuit of the buck DC-DC converter often requires to employ an external inductor. By adaptively switching the current provided to the external inductor, a stable output voltage can be outputted, while the output power is maintained in a proper range, thus avoiding the affection caused by a load effect.
The electric operation principle and structure of a current mode buck DC-DC converter can be learnt by referring to the teaching article issued on the following website http://www.maxim-ic.com/appnotes.cfm/an_pk/2031/, which is provided by Maxim Integrated Products Co.
The function of a conventional current mode buck DC-DC converter is to be schematically illustrated herebelow. FIG. 1 is a block diagram for illustrating a part of functions of the conventional current mode buck DC-DC converter. Referring to FIG. 1, the architecture as shown in FIG. 1 is similar to the examples given in the above-cited website, while only a part of circuitry blocks are illustrated. As shown in FIG. 1, the current mode buck DC-DC converter includes an error amplifier 10, a current comparator 20, a switching unit 30, a driving unit 40, and a current sensing unit 50, and provides an output power source having a suitable output voltage to a load 60.
The error amplifier 10 receives a reference voltage signal Vref and a feedback signal Vfb. The error amplifier 10 are respectively coupled to a negative input terminal and a positive input terminal of the error amplifier, and amplifies a difference between the reference voltage signal Vref and the feedback signal Vfb to obtain an error amplification signal Vea. The current comparator receives the error amplification signal Vea and a current sensing signal Vcs, and is respectively coupled to a negative input terminal and a positive input terminal of the current comparator 20, and generates a reset signal Vrst.
The switching unit 30 can be an RS flip-flop. The switching unit receives an oscillation signal Vosc and the reset signal Vrst, and is respectively coupled to a setting terminal S and a reset terminal R. The switching signal 30 has a positive output terminal Q and a negative output terminal Q′, and generates a positive switching signal Sin at the positive output terminal Q and generates a negative switching signal Sin′ at the negative output terminal Q′. The driving unit 40 receives the positive switching signal Sin and the negative switching signal Sin′, and generates an output signal. The current sensing unit 50 receives the output signal from the driving unit 40, and generates the current sensing signal Vcs.
The driving unit 40 can include two power transistors (not shown in the drawing). The gates of the two power transistors are respectively coupled to the positive switching signal Sin and the negative switching signal Sin′. The drains of the two power transistors are coupled to the load 60 for providing the input power source. In such a way, the input power source of the load 60 can be controlled by the positive switching signal Sin and the negative switching signal Sin′, and the output signal of the driving unit 40 is related to the current flowing through the load 60.
Generally, the reference voltage signal Vref is a stable voltage which is relatively temperature-irrelevant and provided by a reference circuit. Specifically, the reference voltage signal Vref is usually a 1.22V voltage generated by a bandgap circuit. The feedback signal Vfb is adapted for providing a feedback mechanism, for stabilizing the input power source to be provided to the load 60. Generally, two resistances are serially connected together and are then parallel coupled to the power source input terminal of the load 60, and a voltage at where the two resistances are serially connected is taken serving as the feedback signal Vfb. The oscillation signal Vosc is a square wave or an oblique wave having a constant frequency. The oscillation signal Vosc is typically generated by an oscillator.
FIG. 2 is a schematic diagram illustrating an operation wave of a conventional buck DC-DC converter. As shown in FIG. 2, at the beginning, the positive switching signal Sin is at a high level. When the current sensing signal Vcs is greater than the error amplification signal Vea, i.e., the first point A in FIG. 2, the current comparator 20 generates a reset signal Vrst at a high level, and correspondingly the positive switching signal is switched to a low level. When the driving unit 40 receives the positive switching signal Sin at low level (and the negative switching signal Sin′ at high level), and it refreshes the current sensing signal Vcs to a low voltage, e.g., 0V or substantially 0V, via the current sensing unit 50.
However, the current sensing signal Vcs often has a peak voltage, as shown as the second point B in FIG. 3. Along with the timeline, the current sensing signal Vcs drops down to the first voltage V1 at the third point C, and then rises up. In this case, as shown I FIG. 3, the peak voltage at the second point B is greater than the error amplification signal Vea, the current comparator 20 outputs the high level reset signal Vrst in advance. Then, the switching unit 30 generates a low level positive switching signal Sin, and then the driving unit 40 and the current sensing unit 50 refresh the current sensing signal Vcs to a low voltage, such that an average power at the load is reduced down, even to zero.
In accordance with a solution provided by the conventional technology, a leading edge blanking (LEB) signal having a fixed width W1 is introduced. Specifically, within the width W1 of the LEB signal, the switching unit 30 does not generate the low level positive switching signal Sin, or the driving signal 40 and the current sensing unit 50 neglect the low level positive switching signal Sin generated by the switching unit 30, so that the previous electric operation is maintained. In such a way, the misoperation of refreshing the current sensing signal Vcs to the low voltage in advance can be avoided. As shown in FIG. 3, at the edge of the width W1 of the LEB signal, i.e., the fourth point D, the current sensing signal Vcs has a voltage smaller than the error amplification signal Vea. As such, the solution can solve the foregoing difficulty.
However, if there is a residue of the peak current of the current sensing signal Vcs greater than the error amplification signal Vea remained outside of the width of the LEB signal, the switching unit 30, the driving unit 40, or the current sensing unit 50 would still start the misoperation of refreshing the current sensing signal Vcs to the low voltage in advance. As shown by the dashed line waveform of the current sensing signal Vcs, at the edge of the width W1 of the LEB signal, i.e., the fifth point E, the voltage of the current sensing signal Vcs is greater than the error amplification signal Vea. As such, at the fifth point E, the switching unit 30, the driving unit 40, or the current sensing unit 50 would still start the misoperation.
Although an LEB signal having a widened width W1 can be used to solve the foregoing difficulty, it may exceed the time point that the current sensing signal Vcs is equal to the error amplification signal Vea, thus causing a delay of refreshing the current sensing signal Vcs, which may further cause the load power exceeding the predetermined value. The LEB signal having a widened width W1 may even cause a failure of refreshing the current sensing signal Vcs to the low voltage, so that the current sensing signal Vcs remains rising, and the switching function is disabled. Such a malfunction often leads to a permanent damage to the buck DC-DC converter.
Accordingly, an MLEB signal generator is desired for generating an optimal adjustable blanking width, so as to assure that the peak voltage won't cause any misoperation, and the current sensing signal Vcs can be regularly refreshed to the low voltage.